Signal speed requirements of an integrated circuit package keep increasing with every new generation of integrated circuit packages. Generally, an integrated circuit package includes an integrated circuit die and a package substrate. The integrated circuit die is generally capable of satisfying its input-output speed requirements. However, the slow advancement in packaging technology places a limitation on the signal transmission speed of the integrated circuit package.
One of the known causes that may limit the signal transmission speed through a package substrate is capacitive coupling between the solder ball pads and a ground plane in the package substrate. For instance, when a signal is being transmitted through a solder ball pad, there may be an electric field fringing towards the ground plane. The fringing electric field may attract electrical charge on the ground plane to get concentrated in one location. The concentrated electrical charge in one location may produce parasitic capacitance that affects the signal being transmitted (i.e., the parasitic capacitance may degrade the electrical performance of the signal being transmitted). For example, the resultant signal may have a small signal bandwidth and a poor insertion/return loss at high frequencies.
It is within this context that the embodiments described herein arise.